目标：
回顾从传统的单芯片引线框架类型到先进的芯片尺寸封装技术，多芯片封装，3D堆叠以及系统封装（SIP）的半导体封装技术的设计、材料和组装工艺。

Overview of the design, material, and assembly process for semiconductor packaging technology from conventional single chip leadframe type to advanced chip scale package, multichip packaging and 3-D stacking, and System in Package (SIP)

回顾电子和微电子组装的历史、发展、材料、设备和工艺，面向SMT入门者和微电子组装工程师/经理/主管以及想了解电子组装所有概念和技术发展的任何工程师。

Provide overview of the history, progress, materials, equipment and process in electronics and microelectronics assembly for beginner SMT and microelectronics assembly engineers and managers /supervisors and other non engineers who want to be familiar with the overall concept and technology progress in electronics assembly

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 时间：待定 两天课程
开课地点：深圳市南山区科技园南区清华研究院
开课地点：上海市天宝路879号上海市电信培训中心B308室
培训费用：会员价：￥2000元/人 非会员价：￥2300元/人  (四人以上团体报名可获得非会员价的8折优惠)

（含教材费、听课费、咨询费、培训证书费、工作午餐费、茶水费，其余食宿交通自理 ）
咨询电话：（0755）8619-6415 8619-6417 8619-6419

联系人:徐桃英、沈丽、董艳、何娟娟、李群、郭艳梅
联络传真：（0755）8619-6453 
E-mail ：train@smte.net

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本课程将涵盖以下主题：

封装技术回顾         主题
 Topics
 

l         半导体晶圆和裸芯片制造和工艺

l         单芯片引线框架封装设计和工艺

l         球栅阵列（BGA）封装设计、材料和工艺

l         倒装焊封装和COB/DCA

l         芯片尺寸和晶圆级封装设计

l         多芯片封装和系统封装

l         晶圆的封装测试和烧录

l         极的组装可靠性

l         目前封装的应用
 

Semiconductor wafer and bare die fabrication and processing
Single chip lead frame package design and process
Ball grid array packaging design, materials and process
Flip chip in package and chip on board/direct chip attach
Chip scale and wafer level package design
Multichip package and system in package
Wafer level and package testing and burn-in
Board level assembly Reliability
Present package uses and applications
 
 
微电子组装基础     
 
l       半导体技术发展和晶圆制造前后端工艺

l      印制线路板和基底制造工艺刚性和韧性基 底，HDI板

l       无源元件和嵌入式无源元件

l       半导体封装类型和组装

l       表面贴装技术（SMT）设备和工艺

l       无铅材料和焊接工艺

l       自动光学检测（AOI），X射线和可视化检测

l        焊点问题和可靠性

  
Semiconductor technology progress and wafer fab front end process
Printed wiring board (PWB) and substrate fabrication process, rigid and flexible substrates, HDI boards
Passive components and embedded passives
Semiconductor packaging types and assembly
Surface mount Technology (SMT), equipment and process
Lead-free material and soldering process
Automated Optical Inspection (AOI), X-ray and visual inspection
Solder joint problems and reliability
 

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讲师—Wayne Koh博士

Wayne Koh博士在美国从事半导体封装和电子组装20多年，在过去10年中，他先后在Motorola和金士顿技术从事电子组装和封装技术、材料和工艺等方面的工作。他是高密度倒装芯片组装，面阵和芯片尺寸封装，3D高密度互联和组装的技术先锋。Koh博士发表了70多篇学术论文和专业论文，参加过各种技术会议的召开讨论，包括SMTA、NEPCON、ICEPT、HDP、APEX、IMAPS和泛太平洋微电子论坛，他在微电子技术方面拥有20多项专利。

Koh博士在华盛顿大学获得化学工程学士学位，在康奈乐大学获得化学工程的硕士和博士学位。他是IEEE、IMAPS和SMTA的会员。

Dr. Wayne Koh has over 20 years experience in semiconductor packaging and electronics assembly in the United States.  He has worked at Motorola and Kingston Technology on electronics assembly and packaging technology, materials and processes in the past 10 years.  He also pioneered in high density flip chip assembly, area array and chip scale packaging, 3-dimensional high density module interconnect and assembly.   Dr Koh has published over 70 papers and presentations, presented short courses and workshops in technical conferences including SMTA, NEPCON, ICEPT, HDP, APEX, IMAPS, and Pan Pacific Microelectronics Symposium.  He has been awarded over 20 patents in microelectronics technology. 

Dr Koh received his BS in Chemical Engineering from University of Washington and MS and PhD in Chemical Engineering from Cornell University.  He is a member of IEEE, IMAPS, and SMTA.