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Semiconductor Design Standard for Flip Chip Applications

运行环境： Win9x/NT/2000/XP/2003		文件大小： 502 K
软件等级： ★★★		软件类别：其他
开发商：佚名		软件语言：英文
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软件添加：审核:smt2000 录入:smt2000		添加时间： 2005-10-14 14:44:59

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Table of Contents
1 SCOPE......................................................................... 1
1.1 Purpose................................................................. 1
1.2 Classifications ..................................................... 1
1.2.1 Bump Process Technologies................................ 1
1.2.2 Substrate Technologies ....................................... 1
1.2.3 Application Classes.............................................. 1
1.2.4 Producibility Level .............................................. 1
1.3 Presentation .......................................................... 2
1.4 Interpretation ........................................................ 2
1.5 Organization of Design Information ................... 2
1.6 Order of Precedence ........................................... 2
2 APPLICABLE DOCUMENTS...................................... 3
3 DESIGN CONSIDERATIONS ..................................... 3
3.1 Terms and Definitions.......................................... 3
3.2 General ................................................................. 3
3.3 Footprint Design .................................................. 3
3.4 Electrical Considerations .................................... 6
3.4.1 Interconnect Parasitics ......................................... 6
3.4.2 Power and Ground Bumps .................................. 6
3.4.3 Redistribution Effects .......................................... 8
3.4.4 Electromagnetic Radiation................................... 9
3.4.5 Electrical Bias Created by Non-Electrical
Phenomena ......................................................... 10
3.5 Reliability Considerations ................................ 10
3.5.1 General ............................................................... 10
3.5.2 Thermal Fatigue................................................. 10
3.5.2.1 Distance to Neutral Point (DNP) ...................... 10
3.5.3 Electromigration................................................. 11
3.5.4 Thermomigration................................................ 11
3.5.5 Metal Migration ................................................. 11
3.5.6 Corrosion............................................................ 11
3.5.7 Thermal Shock Resistance................................. 11
3.5.8 Creep .................................................................. 11
3.5.9 Alpha Particle Sensitivities................................ 11
3.6 Thermal Considerations..................................... 13
3.7 Application Considerations................................ 13
3.8 Test and Known Good Die Considerations ...... 15
3.9 Process Descriptions ......................................... 15
3.9.1 Process A – Evaporation.................................... 15
3.9.1.1 Process A – Bump Placement and Pad
Design ................................................................ 15
3.9.1.2 Process A – Passivation..................................... 17
3.9.1.3 Process A – Wafer Diameter and Thickness..... 17
3.9.1.4 Process A – Fiducials and Test Structures ........ 17
3.9.1.5 Process A – Die Edge and Scribe Streets ......... 18
3.9.2 Process B – Solder Paste Deposition .............. 18
3.9.2.1 Process B – Bump Placement and Pad
Design ................................................................ 18
3.9.2.2 Process B – Passivation..................................... 19
3.9.2.3 Process B – Wafer Diameter and Thickness .... 20
3.9.2.4 Process B – Fiducials and Test Structures........ 20
3.9.2.5 Process B – Die Edge and Scribe Streets......... 22
3.9.3 Process C – Electroplated Tin-Lead Solder .... 23
3.9.3.1 Process C – Bump Placement and Pad
Design ................................................................ 23
3.9.3.2 Process C – Passivation..................................... 23
3.9.3.3 Process C – Wafer Diameter and Thickness .... 25
3.9.3.4 Process C – Fiducials and Test Structures........ 25
3.9.3.5 Process C – Die Edge and Scribe Streets......... 25
3.9.4 Process D – Gold Stud Bumping (under
consideration) .................................................... 25
3.9.5 Process E – Conductive Epoxy (under
consideration) .................................................... 25
3.9.6 Process F – Electroless Nickel with Solder
Paste Deposition ................................................ 25
3.10 Design Rules ...................................................... 26
Design Rule 1 .................................................... 26
Design Rule 2 .................................................... 26
Design Rule 3 .................................................... 26
Design Rule 4 .................................................... 26
Design Rule 5 .................................................... 27
Design Rule 6 .................................................... 27
Design Rule 7 .................................................... 27
Design Rule 8 .................................................... 27
Design Rule 9 .................................................... 28
Design Rule 10 .................................................. 28
Design Rule 11 ..................................................28
.......

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